AM3715CUSA

Sitara 处理器：Arm Cortex-A8、3D 图形、摄像机

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1 AM3715, AM3703 Sitara ARM Microprocessors

1.1 Features

? AM3715/03 Sitara ARM Microprocessors:

– Compatible with OMAP? 3 Architecture

– Sitara? ARM? Microprocessor (MPU)Subsystem

? Up to 1-GHz Sitara? ARM? Cortex?-A8 Core

 Also supports 300, 600, and 800-MHz operation

? NEON? SIMD Coprocessor

– POWERVR SGX? Graphics Accelerator (AM3715 only)

? Tile Based Architecture Delivering up to 20 MPoly/sec

? Universal Scalable Shader Engine:Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality

? Industry Standard API Support:OpenGLES 1.1 and 2.0, OpenVG1.0

? Fine Grained Task Switching, Load Balancing, and Power Management

? Programmable High Quality Image Anti-Aliasing

– External Memory Interfaces:

? SDRAM Controller (SDRC)

– 16, 32-bit Memory Controller With 1G-Byte Total Address Space

– Interfaces to Low-Power SDRAM

– SDRAM Memory Scheduler (SMS) and Rotation Engine

? General Purpose Memory Controller(GPMC)

– 16-bit Wide Multiplexed Address/Data Bus

– Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin

– Glueless Interface to NOR Flash,NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM

– Flexible Asynchronous Protocol Control for Interface to Custom Logic(FPGA, CPLD, ASICs, etc.)

– Nonmultiplexed Address/Data Mode(Limited 2K-Byte Address Space)

– 1.8-V I/O and 3.0-V (MMC1 only),0.9-V to 1.2-V Adaptive Processor Core Voltage 

0.9-V to 1.1-V Adaptive Core Logic Voltage Note: These are default Operating

Performance Point (OPP) voltages and could be optimized to lower values using

SmartReflex AVS.

– Commercial, Industrial, and Extended

   Temperature Grades

– Serial Communication

? 5 Multichannel Buffered Serial Ports(McBSPs)

– 512 Byte Transmit/Receive Buffer(McBSP1/3/4/5)

– 5K-Byte Transmit/Receive Buffer(McBSP2)

– SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations

– Direct Interface to I2S and PCM Device and T Buses

– 128 Channel Transmit/Receive Mode

? Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports

? High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface)

? High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem

– 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface

? One HDQ/1-Wire Interface

? Four UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared

[CIR] Modes)

? Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers

– Camera Image Signal Processing (ISP)

? CCD and CMOS Imager Interface

? Memory Data Input

? BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface

? Glueless Interface to Common Video Decoders

? Resize Engine

– Resize Images From 1/4x to 4x

– Separate Horizontal/Vertical Control

– System Direct Memory Access (SDMA) 

– System Direct Memory Access (SDMA) Configurable Priority）

– Comprehensive Power, Reset, and Clock Management

? SmartReflexTM Technology

? Dynamic Voltage and Frequency Scaling （DVFS)

– Sitara? ARM? Cortex?-A8 Core

? ARMv7 Architecture

– TrustZone?

– Thumb? -2

– MMU Enhancements

? In-Order, Dual-Issue, Superscalar Microprocessor Core

? NEON Multimedia Architecture

? Over 2x Performance of ARMv6 SIMD

? Supports Both Integer and Floating Point SIMD

? Jazelle? RCT Execution Environment Architecture

? Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack

? Embedded Trace Macrocell (ETM)

Support for Non-Invasive Debug

– ARM Cortex-A8 Memory Architecture:

? 32K-Byte Instruction Cache (4-Way Set-Associative)

? 32K-Byte Data Cache (4-WaySet-Associative)

? 256K-Byte L2 Cache 

– 32K-Byte ROM

– 64K-Byte Shared SRAM

– Endianess:

? ARM Instructions - Little Endian

? ARM Data – Configurable

? Removable Media Interfaces:

– Three Multimedia Card (MMC)/ Secure Digital(SD) With Secure Data I/O (SDIO)

? Test Interfaces

– IEEE-1149.1 (JTAG) Boundary-Scan Compatible

– Embedded Trace Macro Interface (ETM)

– Serial Data Transport Interface (SDTI)

? 12 32-bit General Purpose Timers

? 2 32-bit Watchdog Timers

? 1 32-bit Secure Watchdog Timer

? 1 32-bit 32-kHz Sync Timer

? Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)

? 45-nm CMOS Technology

? Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)

? Packages:

– 515-pin s-PBGA package (CBP Suffix), .5mm Ball Pitch (Top), .4mm Ball Pitch (Bottom)

– 515-pin s-PBGA package (CBC Suffix), .65mm Ball Pitch (Top), .5mm Ball Pitch (Bottom)

– 423-pin s-PBGA package (CUS Suffix), .65mm Ball Pitch

1.2 Applications

This balance of performance and power allow the device to support the following example applications:

? Portable Data Terminals

? Navigation

? Auto Infotainment

? Gaming

? Medical Imaging

? Home Automation

? Human Machine Interface

? Industrial Control

? Test and Measurement

? Single-board Computer

1.3 Description

The AM37x generation (AM3715/AM3703) of Sitara? high-performance microprocessors is based on the enhanced Cortex?-A8 device architecture and is integrated on TI s advanced 45-nm process technology. This architecture is designed to provide best in class ARM and graphics performance while delivering low power consumption.

The device can support numerous high-level operating systems and real-time operating system solutions including Linux, Android and Windows Embedded CE which are available free of charge directly from TI. Additionally, the device is fully backward compatible with previous Cortex-A8 Sitara microprocessors and OMAP? processors.

The AM3715/AM3703 microprocessor data manual presents the electrical and mechanical specifications for the AM3715/AM3703 microprocessor.

The information contained in this data manual applies to both the commercial and extended temperature versions of the AM3715/03 Microprocessor unless otherwise indicated. It consists of the following sections:

? A description of the AM3715/03 terminals: assignment, electrical characteristics, multiplexing, and functional description;

? A presentation of the electrical characteristics requirements: power domains, operating conditions, power consumption, and dc characteristics;

? The clock specifications: input and output clocks, DPLL and DLL;

? A description of thermal characteristics, device nomenclature, and mechanical data about the available packaging