芯云购商城
搜索关键词不能为空
搜索关键词不能为空
收缩

QQ在线咨询

电话咨询

  • 0755-82579613

Skype 咨询

  • 3003361628@qq.com

SN74AHCT125DR_TI(德州仪器)中文资料_英文资料_价格_PDF手册

2024/7/4 14:56:11

211

SN74AHCT125DR

具有 TTL 兼容型 CMOS 输入和三态输出的 4 通道、4.5V 至 5.5V 缓冲器

 

 


                                                        多技术详情请登录www.mroic.cn  

 

 

 

 

· Inputs Are TTL-Voltage Compatible

· Latch-Up Performance Exceeds 250 mA Per JESD 17

· ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

 

 

                               

 

 

description/ordering information

 

 

The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.

 

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.