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SN74AHCT125PWRG4_TI(德州仪器)中文资料_英文资料_价格_PDF手册

2024/6/26 11:59:54

283

SN74AHCT125PWRG4

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

 

 


                                               更多技术详情请登录www.mroic.cn       

 

 

 

• Inputs Are TTL-Voltage Compatible

• Latch-Up Performance Exceeds 250 mA Per JESD 17

• ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

 

 

                 

 

 

description/ordering information

 

The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.

 

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.