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SN74LVTH125RGYR_TI(德州仪器)中文资料_英文资料_价格_PDF手册

2024/6/25 11:38:17

182

SN74LVTH125RGYR

具有总线保持、TTL 兼容型 CMOS 输入和三态输出的 4 通道、2.7V 至 3.6V 缓冲器

 

 

     

                                               更多技术详情请登录www.mroic.cn      

 

 

 

 

· Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)

· Support Unregulated Battery Operation Down to 2.7 V 

· Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 3.3 V, TA = 25°C

· Ioff and Power-Up 3-State Support Hot Insertion

· Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

· Latch-Up Performance Exceeds 500 mA Per JESD 17

· ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

 

 

                            

 

 

description/ordering information

 

These bus buffers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.

 

The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE) input is high.