ADC16V130CISQX/NOPB

Converter With LVDS Outputs

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FEATURES

? Dual Supplies: 1.8V and 3.0V Operation

? On Chip Automatic Calibration During Power-Up

? Low Power Consumption

? Multi-Level Multi-Function Pins for CLK/DF and PD

? Power-Down and Sleep Modes

? On Chip Precision Reference and Sample-and-Hold Circuit

? On Chip Low Jitter Duty-Cycle Stabilizer

? Offset Binary or 2 s Complement Data Format

? Full Data Rate LVDS Output Port

? 64-pin WQFN Package (9x9x0.8, 0.5mm Pin-Pitch)

KEY SPECIFICATIONS

? Resolution: 16 Bits

? Conversion Rate: 130 MSPS

? SNR

– (fIN = 10MHz): 78.5 dBFS (Typ)

– (fIN = 70MHz): 77.8 dBFS (Typ)

– (fIN = 160MHz): 76.7 dBFS (Typ)

? SFDR

– (fIN = 10MHz): 95.5 dBFS (Typ)

– (fIN = 70MHz): 92.0 dBFS (Typ)

– (fIN= 160MHz): 90.6 dBFS (Typ)

? Full Power Bandwidth: 1.4 GHz (Typ)

? Power Consumption

– Core: 650 mW(Typ)

– LVDS Driver: 105 mW (Typ)

– Total: 755 mW (Typ)

? Operating Temperature Range: -40°C ~ 85°C

APPLICATIONS

? High IF Sampling Receivers

? Multi-carrier Base Station Receivers

– GSM/EDGE, CDMA2000, UMTS, LTE, and WiMax

? Test and Measurement Equipment

? Communications Instrumentation

? Data Acquisition

? Portable Instrumentation

DESCRIPTION

The ADC16V130 is a monolithic high performance CMOS analog-to-digital converter capable of converting analog input signals into 16-bit digital words at rates up to 130 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on chip sample-and-hold circuit to minimize power consumption and external component count while providing excellent dynamic performance. Automatic power-up calibration enables excellent dynamic performance and reduces part-to-part variation, and the ADC16V130 could be re-calibrated at any time by asserting and then de-asserting power-down. An integrated low noise and stable voltage reference and differential reference buffer amplifier easies board level design. On-chip duty cycle stabilizer with low additive jitter allows wide duty cycle range of input clock without compromising its dynamic performance.A unique sample-and-hold stage yields a full-power bandwidth of 1.4 GHz. The digital data is provided via full data rate LVDS outputs – making possible the 64-pin, 9mm x 9mm WQFN package. The ADC16V130 operates on dual power supplies 1.8V and 3.0V with a power-down feature to reduce the power consumption to very low levels while allowing fast recovery to full operation.